This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-274434, filed on Sept. 11, 2000; the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a high breakdown voltage device and especially to the protection against electro-static discharge (ESD) on a Lateral Double Diffusion MOSFET (LDMOS).
In general, power IC devices are realized by a low-voltage device and a high breakdown voltage device and they are widely used in the automobile industries or the like. A vehicle-mounted semiconductor device is operated under hostile environments. It is hence necessary to protect the semiconductor device for this purpose in a relatively high level against electric transient phenomena such as electro-static discharge (ESD).
The ESD is considered to be a high-energy pulse which is generated when a person or a material charged comes in contact with the IC device. As one of possible methods of protecting the semiconductor device from ESD, such a configuration is considered that a resistor element is inserted between a semiconductor element and an output terminal (pin) to lower a high voltage level. However, a LDMOS, which is a high breakdown voltage device, is desired to have both a lower level of ON resistance and a high level of breakdown voltage. Accordingly, when the resistor element is provided, the characteristic of the ON resistance of the LDMOS based on pads will adversely be affected, when viewed from a pad.
FIG. 11 illustrates a convention n-type LDMOS formed on a silicon on insulator (SOI) substrate. The SOI substrate comprises a silicon base substrate 11, an n-type silicon layer 13, and an SiO2 layer 12 interposed between the base substrate 11 and the layer 13. Provided selectively in the active layer 13 is a p-type base layer 14. The p-type base layer 14 contains an n+-type source layer 15 and a p+-type diffusion layer 14a. An n+-type drain layer 16 is formed at a portion of the active layer 13 which is spaced from the base layer 14. A LOCOS oxide film 17 is formed in a surface region of the active layer 13 between the drain layer 16 and the base layer 14. A gate electrode (G) 18 is formed above the active layer 13 and the base layer 14 positioned between the source layer 15 and the LOCOS oxide film 17 as separated from the SOI substrate via a gate oxide layer (not shown). A source electrode (S) 19 is formed above the source layer 15 and the p+-type diffusion layer 14a while a drain electrode (D) 20 is formed above the drain layer 16.
When a high intensity of electric field is applied on the drain layer 16 by ESD, an avalanche breakdown occurs at an edge of the drain layer 16 on the side of the LOCOS oxide film 17, thereby generating electrons and holes. The electrons generated at the edge of the drain layer 16 flow into the drain layer 16 while the hole current flows into the base layer 14. If this hole current exceeds a predetermined value, a parasitic bipolar transistor composed of the n-type drain layer 16, the p-type base layer 14, and the n-type source layer turns on. As the parasitic bipolar transistor turns on, the voltage between the source layer and the drain layer is clamped to a low voltage level. However, at the edge of the drain layer, current is locally intensified and a thermal runaway will occur. As a result, the drain layer is declined in the resistance to ESD and may finally be destructed.
A semiconductor device according to an embodiment of the present invention comprises:
an active layer of a first conductive type;
a base layer of a second conductive type selectively formed on a surface region of said active layer;
a source layer of the first conductive type selectively formed on a surface region of said base layer;
an anode layer of the second conductive type selectively formed on a surface region of the active layer, said anode layer being spaced from said base layer;
a drain layer of the first conductive type formed on a surface region between said base layer and said anode layer;
a resistive layer of the first conductive type formed on a surface region between said base layer and said drain layer; and
a gate electrode formed above a region of said base layer between said source layer and said active layer, a gate insulating film being disposed between said base layer and said gate electrode, wherein
a source electrode is formed on the surface of the base layer and the source layer while a drain electrode is formed on the surface of the drain layer and the anode layer.
A semiconductor device according to another embodiment of the present invention comprises:
a first device of lateral DMOS type including
a first active layer of the first conductive type,
a first base layer of the second conductive type formed in said first active layer,
a first source layer of a first conductive type formed in said first base layer,
an anode layer of a second conductive type formed in said first active layer so as to be spaced from the first source layer,
a first drain layer of the first conductive type provided next to said anode layer,
a resistive layer of the first conductive type provided next to said drain layer, and
a first gate layer formed above a region between said first source layer and said resistive layer via a gate insulating film;
a second device of lateral DMOS type including
a second base layer of the second conductive type formed in said first active layer,
a second source layer of the first conductive type formed in the second base layer,
a second drain layer of the first conductive type formed in a second active layer so as to be spaced from the second source layer, and
a second gate layer formed above a region of the second base layer between the second source layer and the second drain layer as separated by a gate insulating film;
a source electrode for electrically connecting between the first source layer and the second source layer;
a drain electrode for electrically connecting between the first drain and drain layers and the second drain layer; and
a gate electrode for electrically connecting between the first gate layer and the second gate layer.